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1 features q 15 to 75 mhz shift clock support q low power consumption q power-down mode <216 m w (max) q cold sparing all pins q narrow bus reduces cable size and cost q up to 1.575 gbps throughput q up to 197 megabytes/sec bandwidth q 325 mv (typ) swing lvds devices for low emi q pll requires no external components q rising edge strobe q radiation-hardened design; total dose irradiation testing to mil-std-883 method 1019 - total-dose: 300 krad(si) and 1 mrad(si) - latchup immune (let > 1 00 m ev-cm 2 /mg) q packaging options: - 48 -lead flatpack q standard microcircuit drawing 5962-01534 - qml q and v compliant part q compatible with tia/eia-644 lvds standard introduction the ut54lvds 217 serializer converts 21 bits of cmos/ttl data into three lvds (low voltage differential signaling) data streams. a phase-locked transmit clock is transmitted in parallel with the data streams over a fourth lvds link. every cycle of the transmit clock 21 bits of input data are sampled and transmitted. at a transmit clock frequency of 75mhz, 21 bits of ttl data are transmitted at a rate of 525 mbps per lvds data channel. using a 75mhz clock, the data throughput is 1.575 gbit/s (197 mbytes/sec). the ut54lvds217 serializer allows the use of wide, high speed ttl interfaces while reducing overall emi and cable size. all pins have cold spare buffers. these buffers will be high impedance when v dd is tied to v ss . standard products ut54lvds217 serializer d ata sheet june, 2003 t t l p a r a l l e l - t o - l v d s pll power down transmit clock in cmos/ttl inputs 21 data (lvds) clock (lvds) t t l p a r a l l e l - t o - figure 1. ut54lvds 217 serializer block diagram
2 pin description figure 2 . ut54lvds217 pinout ut54lvds 217 48 47 46 45 44 43 42 41 n/c lvds gnd 1 txin4 2 v dd 3 4 5 gnd 6 7 8 v dd 9 10 11 12 13 14 15 16 txin6 txin5 txin7 txin8 txin9 txin10 gnd txin11 txin12 v dd txin13 txin14 17 18 19 20 21 22 23 24 txin15 txin17 txin16 v dd txin19 txin18 gnd gnd txin3 txin2 gnd txin1 txin0 txout0- 40 39 38 37 36 35 34 33 txout0+ txout1- lvds gnd txclk out- txout1+ txout2- lvds v dd txout2+ 32 31 30 29 28 27 26 25 pwr dwn txclk in txin20 txclk out+ lvds gnd pll gnd pll v dd pll gnd pin name i/o no. description txin i 21 ttl level input txout+ o 3 positive lvds differential data output txout- o 3 negative lvds differential data output txclk in i 1 ttl level clock input. the rising edge acts as data strobe. pin name txclk in txclk out+ o 1 positive lvds differential clock output txclk out- o 1 negative lvds differential clock output pwr dwn i 1 ttl level input. assertion (low input) tri- states the clock and data outputs, ensur- ing low current at power down. v dd i 4 power supply pins for ttl inputs and logic gnd i 5 ground pins for ttl inputs and logic pll v dd i 1 power supply pins for pll pll gnd i 2 ground pins for ppl lvds v dd i 1 power supply pin for lvds output lvds gnd i 3 ground pins for lvds outputs txin ut54lvds217 0 1 2 cmos/ ttl 18 19 20 txclk pcb rxout ut54lvds218 0 1 2 18 19 20 rxclk pcb shield gnd clock (lvds) data (lvds) lvds cable media dependent figure 3. ut54lvds217 typical application
3 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. maximum junction temperature may be increased to +175 c during burn-in and lifetest. 3. test per mil-std-883, method 1012. 4. for cold spare mode (v dd = v ss ), v i/o may be 0.3v to the maximum recommended operating v dd + 0.3v. recommended operating conditions symbol parameter limits v dd dc supply voltage -0. 3 t o 4.0v v i/o voltage on any pin 4 -0. 3 t o (v dd + 0.3v) t stg storage temperature -65 to +150 c p d maximum power dissipation 2 w t j maximum junction temperature 2 +150 c q jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10ma symbol parameter limits v dd, p ll v dd, lvds v dd positive supply voltage 3.0 to 3.6 v t c case temperature range - 55 to +125 c v in dc input voltage 0v to v dd
4 dc electrical characteristics 1 (v dd = 3.3v-0.3v ; -55 c < t c < +125 c) notes: 1. current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenc ed to ground. 2. output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction only. only one output should be shorted at a time, do not excee d maximum junction temperature specification. 3. guaranteed by characterization. 4. devices are tested @ 3.6 v only. 5. clock outputs guaranteed by design. 6. post 100krad and 300krad, i ccz = 200 m a. symbol parameter condition min max unit cmos/ttl dc specifications v ih high-level input voltage 2.0 v dd v v il low-level input voltage gnd 0 . 8 v i ih high-level input current v in = 3.6v; v dd = 3.6v -10 +10 m a i il low-level input current v in = 0v; v dd = 3.6v -10 +10 m a v cl input clamp voltage i cl = -18ma -1.5 v i cs cold spare leakage current v in = 3.6v; v dd = v ss -20 +20 m a lvds output dc specifications (out+, out-) v od 5 differential output voltage r l = 100 w (see figure 14) 250 400 mv d v od 5 change in v od between complimentary output states r l = 100 w (see figure 14) 35 mv v os 5 offset voltage r l = 100 w , 1.120 1.410 v d v os 5 change in v os between complimentary output states r l = 100 w 35 mv i oz 4 output three-state current pwr dwn = 0v v out = 0v or v dd -10 +10 ma i csout cold spare leakage current v in =3.6v, v dd = v ss -20 +20 ma i os 2,3 output short circuit current v out + or v out - = 0v 5ma ma supply current i ccl 4 transmitter supply current with loads r l = 100 w all channels (figure 4) cl = 5pf, f = 50mhz 65.0 ma i ccz 4,6 power down current d in = v ss pwr dwn = 0v, f = 0hz 60. 0 m a vos voh vol + 2 --------------------------- = ? ??
5 ac switching characteristics 1 (v dd = 3.0v to 3.6v; ta = -55 c to +125 c) notes: 1. recommend transistion time for txclk in is 1.0 to 6.0 ns (figure 6). 2. guaranteed by characterization. 3. channel to channel skew is defined as the difference between tppos max limit and tppos minimum limit. 4. guaranteed by design. symbol parameter min max unit llht 2 lvds low-to-high transition time (figure 5) 1.5 ns lhlt 2 lvds high-to-low transition time (figure 5) 1.5 ns tppos0 2 transmitter output pulse position for bit 0 (figure 13) -0.18 0.270 ns tppos1 2 transmitter output pulse position for bit 1(figure 13) 1.72 2.17 ns tppos2 2 transmitter output pulse position for bit 2 (figure 13) 3.63 4.08 ns tppos3 2 transmitter output pulse position for bit 3 (figure 13) 5.53 5.98 ns tppos4 2 transmitter output pulse position for bit 4 (figure 13) 7.44 7.89 ns tppos5 2 transmitter output pulse position for bit 5 (figure 13) 9.34 9.79 ns tppos6 2 transmitter output pulse position for bit 6 (figure 13) 11.25 11.70 ns tccs 3 channel to channel skew (figure 7) 0.45 ns tcip txclk in period (figure 8) 13.3 66.7 ns tcih 4 txclk in high time (figure 8) 0.35tcip 0.65tcip ns tcil 4 txclk in low time (figure 8) 0.35tcip 0.65tcip ns tstc 2 txin setup to txclk in (figure 8) 1.0 0.5 ns thtc 2 txin hold to txclk in (figure 8) 0.7 0.5 ns tccd txclk in to txclk out delay (figure 9) 0.5 2.5 ns tplls transmitter phase lock loop set (figure 10) 10 ms tpdd transmitter powerdown delay (figure 12) 100 ns f=75mhz f=75mhz f=75mh z f=75mhz f=75mhz f=75mhz f=75mhz 15mhz 75mhz 15mhz 75mhz
6 ac timing diagrams txclk in txin figure 4. test pattern 80% llht lhlt vdiff vdiff=(txout+) - (txout-) 20% 80% 20% txout+ 100 w txout- 5pf figure 5. ut54lvds217 output load and transition times 90% tcit 10% 90% 10% txclk in tcit figure 6. ut54lvds217 input clock transition time t
7 txout0 txout1 txout2 txclk out tccs vdiff= 0v time figure 7. ut54lvds217 channel-to-channel skew txclk out vdiff= 0v txclk in tccd v dd /2 tcil tcip tcih txclk in v dd /2 tstc thtc hold setup txin 0-20 figure 8. ut54lvds217 setup/hold and high/low times figure 9. ut54lvds217 clock-to-clock out delay notes: 1. measurements at v diff = 0v 2. tccs measured between earliest and latest lvds edges. 3. txclk differential low-high edge. sample on l-h edge v dd /2 v dd /2 v dd /2 v dd /2
8 power down v dd tplls txclk in txclk out / rxclk in vdiff = ov v dd /2 figure 10. ut54lvds217 phase lock loop set time txclk out / rxclk in previous cycle next cycle txin15-1 txin14-1 txin20 txin19 txin18 txin17 txin16 txin15 txin14 txin8-1 txin7-1 txin13 txin12 txin11 txin10 txin9 txin8 txin7 txin1-1 txin0-1 txin6 txin5 txin4 txin3 txin2 txin1 txin0 txout2 / rxin2 txout1 / rxin1 txout0 / rxin0 figure 11. ut54lvds217 parallel ttl data inputs mapped to lvds outputs v dd /2 v dd v dd
9 power down txclk in txout three-state tpdd figure 12. transmitter powerdown delay txclk out / differential previous cycle next cycle txin15-1 txin14-1 txin20 txin19 txin18 txin17 txin16 txin15 txin14 txin8-1 txin7-1 txin13 txin12 txin11 txin10 txin9 txin8 txin7 txin1-1 txin0-1 txin6 txin5 txin4 txin3 txin2 txin1 txin0 txout2 / (single ended) txout1 / single ended txout0 / single ended tppos0 tppos1 tppos2 tppos3 tppos4 tppos5 tppos6 figure 13. lvds output pulse position measurement t clk v dd /2
10 figure 14. driver v od and v os test circuit or equivalent circuit d d in d out- d out+ 2 0p f driver enabled generator 50 w r l = 100 w v od 2 0p f
11 packaging figure 15. 48-lead flatpack 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to vss. 3. lead finishes are in accordance with mil-prf-38535. 4. lead position and colanarity are not measured. 5. id mark symbol is vendor option. 6. with solder, increase maximum by 0.003. 6 4 5 6
12 ordering information ut54lvds217 serializer: ut 54lvds217 - * * * * * device type: ut54lvds217 serializer access time: not applicable package type: (u) = 48-lead flatpack (dual-in-line) screening: (c) = military temperature range flow (p) = prototype flow lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. prototype flow per utmc manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per utmc manufacturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
13 ut54lvds217 serializer: smd 5962 - * * * federal stock class designator: no options total dose (r) = 1e5 rad(si) (f) = 3e5 rad(si) (g) = 5e5 rad(si) (contact factory for availability) (h) = 1e6 rad(si) (contact factory for availability) drawing number: 01534 device type 01 = 50mhz lvds serializer (contacat factory) 02 = 75mhz lvds serializer class designator: (q) = qml class q (v) = qml class v case outline: (x ) = 48 lead flatpack (dual-in-line) lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) 01534 ** notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.

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